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ADE7754
MMODE
LVAENERGY[23:0]
REGISTER BIT 4
23
0
FROM VA
ADC
LPF1
ZERO-CROSS
DETECT
ACCUMULATE APPARENT POWER
DURING LINCYC ZERO CROSSINGS
48
0
MMODE
REGISTER BIT 5
FROM VB
ADC
LPF1
ZERO-CROSS
DETECT
CALIBRATION
CONTROL
APPARENT
POWER
PHASE A
APPARENT
POWER
+
+
+
VADIV
48
+
%
0
MMODE
REGISTER BIT 6
LINCYC[15:0]
PHASE B
APPARENT
POWER
+
FROM VC
ZERO-CROSS
PHASE C
ADC
LPF1
DETECT
Figure 39. Apparent Energy Calibration
The number of half line cycles is specified in the LINCYC unsigned
16-bit register. The ADE7754 can accumulate apparent power
for up to 65535 combined half cycles. Because the apparent
power is integrated on the same integral number of line cycles as
the line active energy register, these two values can be compared
easily. See the Energies Scaling section. The active and apparent
energy are calculated more accurately because of this precise
timing control and provide all the information needed for reactive
power and power factor calculation. At the end of an energy
calibration cycle, the LINCYC flag in the interrupt status register
is set. If the LINCYC enable bit in the interrupt enable register
is set to Logic 1, the IRQ output also goes active low. Thus the
IRQ line can also be used to signal the end of a calibration.
The total apparent power calculated by the ADE7754 in the
line accumulation mode depends on the configuration of the
mulation of the apparent energy over half line cycles in the
LVAENERGY is no longer available. See Figure 33. Since the
LVAENERGY register is an unsigned value, the accumulation
of the active energy in the LVAENERGY register is unsigned.
In this mode (reactive energy), the selection of the phases
accumulated in the LAENERGY and LVAENERGY registers
is done by the LWATSEL selection bits of the WATMode
register.
ENERGIES SCALING
The ADE7754 provides measurements of the active, reactive,
and apparent energies. These measurements do not have the
same scaling and thus cannot be compared directly to each other.
Energy
VAMOD bits in the VAMode register. Each term of the formula
Type
PF = 1
PF = 0.707
PF = 0
used can be disabled or enabled by the LVASEL bits of the
VAMode register. The different configurations are described in
Table VI.
Activ e Wh
Reactiv e 0
Wh
Wh
0.707
0.707 / 9.546
0
Wh / 9.546
Table VI. Total Line Apparent Energy Calculation
Apparen t Wh / 3.657
CHECK SUM REGISTER
Wh / 3.657
Wh / 3.657
VAMOD VASEL0
VASEL1
VASEL2
The ADE7754 has a checksum register (CHECKSUM[5:0]) to
0d
1d
2d
V ARMS × I ARMS
V ARMS × I ARMS
V ARMS × I ARMS
+ V BRMS × I BRMS
+(V ARMS + V CRMS )
/2 × I BRMS
+ V ARMS × I BRMS
+ V CRMS × I CRMS
+ V CRMS × I CRMS
+ V CRMS × I CRMS
ensure that the data bits received in the last serial read operation
are not corrupted. The 6-bit checksum register is reset before
the first bit (MSB of the register to be read) is put on the
DOUT pin. During a serial read operation, when each data bit
becomes available on the rising edge of SCLK, the bit is added
to the checksum register. In the end of the serial read operation,
The line apparent energy accumulation uses the same signal
path as the apparent energy accumulation. The LSB size of
these two registers is equivalent.
The ADE7754 accumulates the total reactive power signal in
the LAENERGY register. This mode is selected by setting to
Logic 1 Bit 5 of the WAVMode register (Address 0Ch). When
the content of the checksum register will equal the sum of all
ones in the register previously read. Using the checksum regis-
ter, the user can determine whether an error has occurred during
the last read operation. Note that a read to the checksum register
also generates a checksum of the checksum register itself.
this bit is set, the accumulation of the active energy over half
line cycles in the LAENERGY register is disabled and done
CONTENT OF REGISTER (n-BYTES)
DOUT
instead in the LVAENERGY register. In this mode, the accu-
CHECKSUM
REGISTER
ADDR: 3Eh
Figure 40. Checksum Register for Serial Interface Read
REV. 0
–27 –
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